10 Gigabit Ethernet TCP Frame Data Registration Algorithm Based on FPGA

Abstract

Using FPGA to achieve full hardware protocol stack in 10 Gigabit Ethernet(10GigE) has the following advantages, such as low cost, wide range of application, high efficiency, etc. Compared with gigabit Ethernet, 10GigE adopts wider data width, which makes hardware face the difficulty of data registration for handling intra-frame data. This paper designed “FIFO form circular-queue handling TCP frame data registration algorithmâ€, solved the problem of data registration when FPGA device receives, stores and sends TCP frame data and adopted FPGA to build practical system to realize TCP through hard core coding. At the same time, this algorithm can also be used for the data registration of other protocol in 10GigE environments.