Design and Realisation of DDR2 SDRAM Controller for Image Real-time Processing Based on FPGA

Si-min GUAN, Fan-liang BU, Guang-di LIU

Abstract


According to the needs of real-time cache, high-rate storage and reading data of image processing system, this paper designs a kind of DDR2 SDRAM controller and introduces the system architecture and data channel of DDR2 controller. The function module of DDR2 controller is designed by using Verilog HDL through the modular design pattern. Then the function of each module and the configuration of core IP are described in detail. Finally, the simulation result of DDR2 controller proves that it can be well applied to the image processing system based on FPGA.

Keywords


FPGA, DDR2 SDRAM, Verilog HDL, Quartus II.


DOI
10.12783/dtcse/mcsse2016/10976

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