A Novel Methodology on Optimizing the Performance of Multi-core Processor Using FPGA

Abstract

With rapid progress in microelectronic technology and higher performance requirements, multi-core processors (MP) have become widely used in various applications. Among them, multiprocessor System-on-Chip (MPSoC) received focus because of its high integration level and low power solution. This work proposed more efficient way to implement MPSoC with higher performance. Synchronous data flow (SDF) is used to model high-speed MPSoC systems, and to simulate the system level functional algorithms. After building a suitable FPGA platform architecture, we prototype these SDF graphs onto FPGA based MPSoC platform. Simulation results show that the MPSoC platform has higher performance than a single processor platform, with novel architecture and scheduling strategy used. Furthermore, different scheduling strategies, including static order and run-time order, are compared on MPSoC. The results have shown that the optimized static order strategy can achieve higher performance than run-time order strategy, with less buffer cost.