Improving the Performance of a Power Hardware-In-the-Loop System by a New Interface Algorithm

Abstract

Power Hardware-In-the-Loop (PHIL) is an efficient way to analysis and test electrical equipment which is introduced into power system. To improve the performance of a PHIL system, the feasibility of several interface algorithms for PHIL system are analyzed. And a new interface algorithm, which is based on the virtual impedance method (VIM), is proposed. Therefore, the proposed interface algorithm is compared and assessed with the current interface algorithms. Through the comparing and testing, the proposed interface algorithm is verified that it obtains a better overall performance than another.