Research on Relationship Between Transistor Size and DC Noise Margin of CMOS Inverter

Abstract

The DC noise margin is used to analyze the maximum noise tolerance on the output of the previous logic gate when the logic gates are connected in series. In order to make a logic gate stable and less sensitive to noise and disturbances, the interval of voltage value represented by logic 0 and logic 1 of input signal should be as large as possible. In this paper, the relationship between Wp-to-Wn ratio and the noise margins of CMOS inverter is studied. Through DC analysis of the transfer characteristics of several inverters with different sizes, the relationship between the switching threshold of CMOS inverters and Wp-to-Wn ratio is obtained. It is concluded that the threshold voltage is closest to VVD/2 when the ratio is 2.3:1.