FPGA Implementation of Machine Learning Hardware Accelerator for Mobile Applications of Brain-Computer Interface

Abstract

Mobile application of brain-computer interface (BCI) system is of great significance. This paper first analyzes machine learning algorithms commonly used in BCI, and extracts QR decomposition as the core step of algorithm integration to design hardware accelerators. Secondly, using Givens Rotation (GR) as implementation strategy of QR decomposition (QRD). Finally, High Level Synthesis (HLS) method is used to synthesize and implement IP cores of QRD in FPGA. QRD based IP cores are designed with floating point and fixed point for 8×8 and 62×62 matrix. Experiments show that resource consumption by fixed point implementation reduce by 40% compared to floating point implementation and speed of operations increase by more than one time. Finally, based on QRD based IP cores, matrix inversion IP cores are designed and implemented, which is at least 3 times faster than ARM Cortex-M3 platform.