The Design and Implementation of Configurable Time-Delay Simulator Based on FPGA

Abstract

A Device of Configurable Time-Delay Simulator is designed and implemented based on FPGA to adapt to the demand of simulating large and real physical time-delay in the laboratory environment. In this paper, the time-delay simulator can be configured the delay time dynamically through the host computer. The Range of the delay time is from 0 seconds to 6 seconds, and the accuracy of the device reaches the nanosecond level. We also discuss the method to measure the delay of the device itself, as well as eliminate system error when we use a computer which is installed a non-real-time operating system, such as Windows or Linux, to take this device into implementation. And the result, which shows that the delay time of the device is 608ns, which is far less than the error introduced using non-real-time systems, can help us revise the configuration parameters.