A FPGA-based Hardware Architecture for Real-time Texture Classification Using Local Binary Patterns

Long Zhang, Wanxia Qu, Yang Guo, Sikun Li

Abstract


Local Binary Pattern (LBP) is a simple yet efficient texture operator which has become a popular approach in texture classification. In this paper, we propose a novel hardware architecture for texture classification algorithms based on local binary patterns that can be executed efficiently on a field-programmable gate arrays (FPGAs). A new memory structure and window operations have been used in this hardware design to accelerate images processing. The new architecture is implemented on Xilinx Virtex-6 FPGA. The experiments show that this new method exhibits more efficient execution compared with standard implementations based on central processing units and graphics processing units.

Keywords


local binary patterns; texture classification; window operations; FPGA


DOI
10.12783/dtetr/iceta2016/6964

Refbacks

  • There are currently no refbacks.